This invention relates to an output buffer circuit in a semiconductor memory device, and more particularly to an output buffer circuit with a preset function for precharging a voltage level of an output pad at a constant level before the next output signal is provided to the output pad to improve data access speed and to reduce noise.
An output buffer circuit in a semiconductor memory device outputs an output signal from a sense amplifier to an output pad and the prior output buffer circuit is shown in FIG. 1. Referring to FIG. 1, the prior output buffer circuit includes a first two-input NAND gate 11 receiving a control signal poe which is an enable signal as a first input signal and an input signal sj from a sense amplifier (not shown) as a second input signal to generate a pull up driving signal dp; a first inverting gate 12 for inverting the input signal sj; a second two-input NAND gate 13 receiving an output signal of the first inventing gate 12 as a first input signal and the control signal poe as a second signal; a second inverting gate 14 for inverting an output signal of the second NAND 12 to generate a pull down driving signal dn; a PMOS transistor 15 being driven by the pull up driving signal dp from the first NAND gate 11; and a NMOS transistor 16 being driven by the pull down driving signal dn. The output buffer circuit generates an output signal out through drains of the PMOS transistor 15 and the NMOS transistor 16 which are commonly connected to each other.
Hereinafter, the operation of the output buffer circuit in FIG.1 will be described with reference to FIG. 2A to FIG. 2C in more detail. If the control signal poe, that is an enable signal is a high state as shown in FIG. 2A, the output buffer circuit is enabled and the level of the output node OUT is determined in accordance with a logic state of the input signal sj. That is, if the input signal sj is a high state, the pull up driving signal dp and the pull down driving signal dn become all low states. The pull up transistor, the PMOS transistor 15 is turned on and the pull down transistor, the NMOS transistor 16 is turned off, so that the output node becomes a high state. If the input signal sj is a low state as shown in FIG. 2b, the pull up driving signal dp and the pull down driving signal dn are all high states. The PMOS transistor 15 is turned off and the NMOS transistor 16 is turned on, so that the output node OUT becomes a low state as shown in FIG. 2C.
On the contrary, if the control signal poe is a low state as shown in FIG. 2A, the output buffer circuit is disabled. If the output buffer circuit becomes disabled, the pull up driving signal becomes a high state and the pull down driving signal becomes a low state. The PMOS transistor 15 and the NMOS transistor 16 are turned off and the output node is floating and then is transited into a high impedance as shown in FIG. 2C.
However, when the capacitance of a load capacitor in the output node is large, next data is generated before the output node is transited into a high impedance and the time for charging and discharging the load capacitor is required so that the access time is increased. Accordingly, the swing of the output signal becomes large to increase current noise.